テストベンチのテクニック集

`timescale 1ns/1ps
`default_nettype none
// Two accumulators with the same arithmetic. good_* is reset, bad_* is not.
// mode has no reset either, which is what hides the defect from the waveform.
module x_demo (
    input  wire       clk,
    input  wire       rst_n,
    input  wire [3:0] din,
    input  wire       set_mode,
    output reg  [3:0] good_sum,
    output reg  [3:0] bad_sum,
    output reg        bad_flag
);
    reg [3:0] good_acc;
    reg [3:0] bad_acc;   // no reset: starts as X in simulation
    reg       mode;      // no reset: starts as X in simulation

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            good_acc <= 4'd0;
            good_sum <= 4'd0;
        end else begin
            good_acc <= good_acc + din;
            good_sum <= good_acc + din;
        end
    end

    always @(posedge clk) begin
        bad_acc <= bad_acc + din;
        bad_sum <= bad_acc + din;
        if (set_mode) mode <= 1'b1;
    end

    // An if statement treats an X condition as false, so bad_flag stays a
    // clean 0 even while mode itself is unknown.
    always @(posedge clk) begin
        if (mode) bad_flag <= 1'b1;
        else      bad_flag <= 1'b0;
    end
endmodule
`default_nettype wire

`timescale 1ns/1ps
`default_nettype none
// This testbench documents three observations about unknown values:
//   1. the reset path matches the specification,
//   2. the unreset path returns X, which !== detects,
//   3. an X condition is hidden behind a clean 0 output.
module tb_x_demo;
    reg clk = 0;
    reg rst_n, set_mode;
    reg [3:0] din;
    wire [3:0] good_sum, bad_sum;
    wire       bad_flag;
    reg  [3:0] expected = 4'd0;
    integer checks = 0;
    reg guard_on = 0;

    x_demo dut(.clk(clk), .rst_n(rst_n), .din(din), .set_mode(set_mode),
               .good_sum(good_sum), .bad_sum(bad_sum), .bad_flag(bad_flag));
    always #5 clk = ~clk;

    task check;
        input [3:0] actual, want;
        begin
            checks = checks + 1;
            if (actual !== want)
                $fatal(1, "FAIL: check=%0d actual=%b want=%h time=%0t",
                       checks, actual, want, $time);
        end
    endtask

    task check_bit;
        input actual, want;
        begin
            checks = checks + 1;
            if (actual !== want)
                $fatal(1, "FAIL: check=%0d actual=%b want=%b time=%0t",
                       checks, actual, want, $time);
        end
    endtask

    // Confirms that a value really is unknown, which is the point of the demo.
    task expect_unknown;
        input [3:0] value;
        begin
            checks = checks + 1;
            if (!$isunknown(value))
                $fatal(1, "FAIL: check=%0d expected an unknown value, got %b time=%0t",
                       checks, value, $time);
        end
    endtask

    // One cycle of stimulus, then compare the reset path with the specification.
    task step;
        input [3:0] value;
        begin
            @(negedge clk);
            din = value;
            @(posedge clk);
            #1;
            expected = (expected + value) & 4'hF;
            check(good_sum, expected);
            expect_unknown(bad_sum);
        end
    endtask

    // Any X on the reset path is a real defect, so stop as soon as one appears.
    always @(posedge clk) begin
        #2 if (guard_on && $isunknown(good_sum))
            $fatal(1, "FAIL: good_sum became unknown (%b) at %0t", good_sum, $time);
    end

    initial begin
        $dumpfile("x_demo.vcd");
        $dumpvars(0, tb_x_demo);
        rst_n = 1; set_mode = 0; din = 4'd0;
        #1 rst_n = 0;
        #1 check(good_sum, 4'd0);          // 1 reset clears the good path
        expect_unknown(bad_sum);           // 2 reset does not reach the bad path
        @(negedge clk); rst_n = 1; guard_on = 1;
        step(4'd3);                        // 3-4
        step(4'd5);                        // 5-6
        step(4'd9);                        // 7-8  wraps at 16
        step(4'd1);                        // 9-10
        // The condition inside the DUT is unknown, yet the output is a clean 0.
        checks = checks + 1;
        if (!$isunknown(dut.mode))
            $fatal(1, "FAIL: check=%0d mode was expected to be unknown", checks);
        check_bit(bad_flag, 1'b0);         // 12 X-optimism hides the unknown mode
        $display("  observed: dut.mode=%b bad_flag=%b bad_sum=%b good_sum=%h",
                 dut.mode, bad_flag, bad_sum, good_sum);
        @(negedge clk); set_mode = 1'b1;
        @(posedge clk); #1;
        check_bit(dut.mode, 1'b1);         // 13 mode is known from now on
        check_bit(bad_flag, 1'b0);         // 14 the flag still used the old mode
        @(posedge clk); #1;
        check_bit(bad_flag, 1'b1);         // 15 the flag follows mode one cycle later
        expect_unknown(bad_sum);           // 16 the unreset adder stays unknown
        $display("PASS: x_propagation (%0d checks)", checks);
        $finish;
    end

    initial begin
        #2000;
        $fatal(1, "FAIL: testbench timeout");
    end
endmodule
`default_nettype wire

出力は変わりません。mode がXのとき mode === 1'b1 は偽に確定するので、どちらでも else 側が実行され bad_flag は0になります。変わるのは意図の伝わり方だけで、Xを見つけられるようにはなりません。=== は4値をそのまま比べる演算子で、合成時の扱いはツールに依存します。Xを見つけたいなら、判定する側（テストベンチ）で $isunknown を使うか、リセットを足して条件を確定させます。