デコーダとエンコーダを書く

`timescale 1ns/1ps
`default_nettype none
// Two BCD to seven-segment decoders that differ only in how they treat
// the inputs 10 to 15, which the specification does not use.
//   seg_hold : no else / no default. The output keeps its previous value.
//   seg_safe : every input is assigned. 10 to 15 blank the display.
// Segment order is {a,b,c,d,e,f,g}, active high.
module seg7_decoder (
    input  wire [3:0] d,
    output reg  [6:0] seg_hold,
    output reg  [6:0] seg_safe
);
    always @* begin
        if (d <= 4'd9) begin
            case (d)
                4'd0: seg_hold = 7'b1111110;
                4'd1: seg_hold = 7'b0110000;
                4'd2: seg_hold = 7'b1101101;
                4'd3: seg_hold = 7'b1111001;
                4'd4: seg_hold = 7'b0110011;
                4'd5: seg_hold = 7'b1011011;
                4'd6: seg_hold = 7'b1011111;
                4'd7: seg_hold = 7'b1110000;
                4'd8: seg_hold = 7'b1111111;
                4'd9: seg_hold = 7'b1111011;
            endcase
        end
        // no else: nothing is assigned for 10 to 15
    end

    always @* begin
        case (d)
            4'd0: seg_safe = 7'b1111110;
            4'd1: seg_safe = 7'b0110000;
            4'd2: seg_safe = 7'b1101101;
            4'd3: seg_safe = 7'b1111001;
            4'd4: seg_safe = 7'b0110011;
            4'd5: seg_safe = 7'b1011011;
            4'd6: seg_safe = 7'b1011111;
            4'd7: seg_safe = 7'b1110000;
            4'd8: seg_safe = 7'b1111111;
            4'd9: seg_safe = 7'b1111011;
            default: seg_safe = 7'b0000000;
        endcase
    end
endmodule
`default_nettype wire

`timescale 1ns/1ps
`default_nettype none
// The expected patterns are written as a plain table here, separately from
// the decoder's case statement, so a copied mistake cannot hide.
module tb_seg7_decoder;
    reg [3:0] d;
    wire [6:0] seg_hold, seg_safe;
    reg [6:0] want [0:9];
    integer checks = 0;
    integer i;

    seg7_decoder dut(.d(d), .seg_hold(seg_hold), .seg_safe(seg_safe));

    task check;
        input [6:0] actual, expected;
        input [8*12-1:0] label;
        begin
            checks = checks + 1;
            if (actual !== expected)
                $fatal(1, "FAIL: check=%0d %0s d=%0d actual=%b expected=%b",
                       checks, label, d, actual, expected);
        end
    endtask

    task drive;
        input [3:0] value;
        begin
            d = value;
            #1;
        end
    endtask

    initial begin
        $dumpfile("seg7_decoder.vcd");
        $dumpvars(0, tb_seg7_decoder);
        want[0] = 7'b1111110; want[1] = 7'b0110000; want[2] = 7'b1101101;
        want[3] = 7'b1111001; want[4] = 7'b0110011; want[5] = 7'b1011011;
        want[6] = 7'b1011111; want[7] = 7'b1110000; want[8] = 7'b1111111;
        want[9] = 7'b1111011;

        // 0 to 9: both decoders follow the specification.
        for (i = 0; i <= 9; i = i + 1) begin
            drive(i[3:0]);
            check(seg_hold, want[i], "hold 0-9");
            check(seg_safe, want[i], "safe 0-9");
        end

        // The same unused input after two different digits.
        drive(4'd9);  drive(4'd10);
        check(seg_hold, want[9], "after 9");       // keeps the pattern for 9
        check(seg_safe, 7'b0000000, "safe after 9");
        $display("  d=10 after 9: seg_hold=%b seg_safe=%b", seg_hold, seg_safe);

        drive(4'd5);  drive(4'd10);
        check(seg_hold, want[5], "after 5");       // keeps the pattern for 5
        check(seg_safe, 7'b0000000, "safe after 5");
        $display("  d=10 after 5: seg_hold=%b seg_safe=%b", seg_hold, seg_safe);

        // 11 to 15 behave the same way.
        for (i = 11; i <= 15; i = i + 1) begin
            drive(4'd3);
            drive(i[3:0]);
            check(seg_hold, want[3], "held pattern");
            check(seg_safe, 7'b0000000, "safe blank");
        end

        $display("PASS: seg7 decoder coverage (%0d checks)", checks);
        $finish;
    end

    initial begin
        #1000;
        $fatal(1, "FAIL: testbench timeout");
    end
endmodule
`default_nettype wire

仕様で決めます。よくあるのは「上位の入力を優先する」で、これを形にしたものが優先順位エンコーダです（応用実験1）。決めずに書くと、記述の順序や if の並びでたまたま決まった動作になり、読む人には意図か偶然か区別できません。テストでも、同時に1になる入力の組合せを試して、決めた優先順位どおりかを確かめてね。このページの5章・6章のエンコーダも、その目で読み直してみよう。