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`timescale 1ns/1ps
`default_nettype none
// A small unit with two data inputs that are NOT interchangeable.
module sub_unit (
    input  wire [3:0] a,
    input  wire [3:0] b,
    input  wire       do_sub,
    output wire [4:0] result
);
    assign result = do_sub ? ({1'b0, a} - {1'b0, b})
                           : ({1'b0, a} + {1'b0, b});
endmodule

// The same unit connected three ways.
module port_connection (
    input  wire [3:0] x,
    input  wire [3:0] y,
    input  wire       do_sub,
    output wire [4:0] r_named,
    output wire [4:0] r_ordered,
    output wire [4:0] r_swapped
);
    // by name: the order in the instance does not matter
    sub_unit u_named (.b(y), .do_sub(do_sub), .a(x), .result(r_named));

    // by position: correct order
    sub_unit u_ordered (x, y, do_sub, r_ordered);

    // by position with the first two swapped: a common slip
    sub_unit u_swapped (y, x, do_sub, r_swapped);
endmodule
`default_nettype wire

`timescale 1ns/1ps
`default_nettype none
// 16 x 16 inputs x add/subtract = 512 patterns.
module tb_port_connection;
    reg [3:0] x, y;
    reg do_sub;
    wire [4:0] r_named, r_ordered, r_swapped;
    reg [4:0] want;
    integer checks = 0;
    integer differ_add = 0;
    integer differ_sub = 0;
    integer i, j;

    port_connection dut(.x(x), .y(y), .do_sub(do_sub),
                        .r_named(r_named), .r_ordered(r_ordered), .r_swapped(r_swapped));

    task check;
        input [4:0] actual, expected;
        input [8*10-1:0] label;
        begin
            checks = checks + 1;
            if (actual !== expected)
                $fatal(1, "FAIL: check=%0d %0s x=%b y=%b do_sub=%b actual=%b expected=%b",
                       checks, label, x, y, do_sub, actual, expected);
        end
    endtask

    initial begin
        $dumpfile("port_connection.vcd");
        $dumpvars(0, tb_port_connection);
        for (i = 0; i < 16; i = i + 1) begin
            for (j = 0; j < 16; j = j + 1) begin
                x = i[3:0]; y = j[3:0];
                do_sub = 1'b0; #1;
                want = i + j;
                check(r_named,   want, "named add");
                check(r_ordered, want, "order add");
                if (r_swapped !== r_ordered) differ_add = differ_add + 1;
                #1;
                do_sub = 1'b1; #1;
                want = {1'b0, i[3:0]} - {1'b0, j[3:0]};
                check(r_named,   want, "named sub");
                check(r_ordered, want, "order sub");
                if (r_swapped !== r_ordered) differ_sub = differ_sub + 1;
                #1;
            end
        end
        x = 4'd9; y = 4'd4; do_sub = 1'b1; #1;
        $display("  9 - 4: named=%0d ordered=%0d swapped=%0d", r_named, r_ordered, r_swapped);
        x = 4'd9; y = 4'd4; do_sub = 1'b0; #1;
        $display("  9 + 4: named=%0d ordered=%0d swapped=%0d", r_named, r_ordered, r_swapped);
        $display("  swapped differs from ordered: add %0d of 256, subtract %0d of 256",
                 differ_add, differ_sub);
        $display("PASS: port connection (%0d checks)", checks);
        $finish;
    end

    initial begin
        #20000;
        $fatal(1, "FAIL: testbench timeout");
    end
endmodule
`default_nettype wire

ポートが少なく、順序が変わる見込みがなく、同じファイル内で完結しているような小さな部品なら、位置接続でも実害は出にくいです。ただし「変わる見込みがない」は人の見積もりなので、部品を共有したり、あとから端子を足したりする場面では名前接続のほうが安全です。この教材では名前接続を基本にします。どちらを使うにしても、上で見たように順番で答えが変わる操作を試験に入れておくことが要ります。