演算回路を書く

`timescale 1ns/1ps
`default_nettype none
// One bit of addition, written out as gates.
module full_adder (
    input  wire a,
    input  wire b,
    input  wire cin,
    output wire sum,
    output wire cout
);
    assign sum  = a ^ b ^ cin;
    assign cout = (a & b) | (a & cin) | (b & cin);
endmodule

// The same 4-bit addition written three ways:
//   rc_*  : ripple carry, four full adders chained
//   cla_* : carry lookahead, carries expanded from generate/propagate
//   ref_* : the + operator, used as the reference
module adder4_styles (
    input  wire [3:0] a,
    input  wire [3:0] b,
    input  wire       cin,
    output wire [3:0] rc_sum,
    output wire       rc_cout,
    output wire [3:0] cla_sum,
    output wire       cla_cout,
    output wire [3:0] ref_sum,
    output wire       ref_cout
);
    // ripple carry
    wire c1, c2, c3;
    full_adder fa0(.a(a[0]), .b(b[0]), .cin(cin), .sum(rc_sum[0]), .cout(c1));
    full_adder fa1(.a(a[1]), .b(b[1]), .cin(c1),  .sum(rc_sum[1]), .cout(c2));
    full_adder fa2(.a(a[2]), .b(b[2]), .cin(c2),  .sum(rc_sum[2]), .cout(c3));
    full_adder fa3(.a(a[3]), .b(b[3]), .cin(c3),  .sum(rc_sum[3]), .cout(rc_cout));

    // carry lookahead
    wire [3:0] g = a & b;          // generate
    wire [3:0] p = a ^ b;          // propagate
    wire k1 = g[0] | (p[0] & cin);
    wire k2 = g[1] | (p[1] & g[0]) | (p[1] & p[0] & cin);
    wire k3 = g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & cin);
    assign cla_cout = g[3] | (p[3] & g[2]) | (p[3] & p[2] & g[1])
                           | (p[3] & p[2] & p[1] & g[0]) | (p[3] & p[2] & p[1] & p[0] & cin);
    assign cla_sum = p ^ {k3, k2, k1, cin};

    // reference
    assign {ref_cout, ref_sum} = a + b + cin;
endmodule
`default_nettype wire

`timescale 1ns/1ps
`default_nettype none
// Drives all 4-bit a, b and cin combinations: 16 x 16 x 2 = 512 patterns.
// Each pattern compares two hand-written adders with the + operator.
module tb_adder4_styles;
    reg [3:0] a, b;
    reg cin;
    wire [3:0] rc_sum, cla_sum, ref_sum;
    wire rc_cout, cla_cout, ref_cout;
    integer checks = 0;
    integer i;

    adder4_styles dut(.a(a), .b(b), .cin(cin),
                      .rc_sum(rc_sum), .rc_cout(rc_cout),
                      .cla_sum(cla_sum), .cla_cout(cla_cout),
                      .ref_sum(ref_sum), .ref_cout(ref_cout));

    task check_ripple;
        begin
            checks = checks + 1;
            if ({rc_cout, rc_sum} !== {ref_cout, ref_sum})
                $fatal(1, "FAIL: ripple a=%b b=%b cin=%b got=%b expected=%b",
                       a, b, cin, {rc_cout, rc_sum}, {ref_cout, ref_sum});
        end
    endtask

    task check_lookahead;
        begin
            checks = checks + 1;
            if ({cla_cout, cla_sum} !== {ref_cout, ref_sum})
                $fatal(1, "FAIL: lookahead a=%b b=%b cin=%b got=%b expected=%b",
                       a, b, cin, {cla_cout, cla_sum}, {ref_cout, ref_sum});
        end
    endtask

    initial begin
        $dumpfile("adder4_styles.vcd");
        $dumpvars(0, tb_adder4_styles);
        $display("   a    b  cin | ripple lookahead   +");
        for (i = 0; i < 512; i = i + 1) begin
            {a, b, cin} = i[8:0];
            #1;
            check_ripple;
            check_lookahead;
            if ((a == 4'd15 && b == 4'd1) || (a == 4'd15 && b == 4'd15) || (a == 4'd8 && b == 4'd8))
                $display("%4d %4d    %b |  %b    %b    %b",
                         a, b, cin, {rc_cout, rc_sum}, {cla_cout, cla_sum}, {ref_cout, ref_sum});
            #1;
        end
        $display("PASS: adder styles (%0d checks)", checks);
        $finish;
    end

    initial begin
        #20000;
        $fatal(1, "FAIL: testbench timeout");
    end
endmodule
`default_nettype wire

和は0になり、桁上げ出力が1になります。上の実行結果で 10000 と表示されているのがその状態で、先頭の1が桁上げ出力です。+ の結果を4ビットの変数だけで受けると、この桁上げは捨てられます。桁あふれを使う回路では、受け側を5ビットにするか、桁上げ出力を別の信号として扱ってね。ビット幅の扱いは文法実験4でも確かめられます。