Verilog基本文法（前編）

`timescale 1ns/1ps
`default_nettype none
// The same expression written three ways. Two of them are combinational
// even though one of those is declared as reg.
module reg_vs_wire (
    input  wire clk,
    input  wire a,
    input  wire b,
    output wire y_assign,   // continuous assignment on a wire
    output reg  y_comb,     // reg assigned in always @*  -> still combinational
    output reg  y_ff        // reg assigned at a clock edge -> a flip-flop
);
    assign y_assign = a & b;

    always @* begin
        y_comb = a & b;
    end

    always @(posedge clk) begin
        y_ff <= a & b;
    end
endmodule
`default_nettype wire

`timescale 1ns/1ps
`default_nettype none
// Changes the inputs between clock edges and watches which outputs follow.
module tb_reg_vs_wire;
    reg clk = 0;
    reg a, b;
    wire y_assign;
    wire y_comb, y_ff;
    reg expected_ff;
    integer checks = 0;
    integer i;

    reg_vs_wire dut(.clk(clk), .a(a), .b(b),
                    .y_assign(y_assign), .y_comb(y_comb), .y_ff(y_ff));
    always #5 clk = ~clk;

    task check;
        input actual, want;
        input [8*12-1:0] label;
        begin
            checks = checks + 1;
            if (actual !== want)
                $fatal(1, "FAIL: check=%0d %0s a=%b b=%b actual=%b want=%b time=%0t",
                       checks, label, a, b, actual, want, $time);
        end
    endtask

    initial begin
        $dumpfile("reg_vs_wire.vcd");
        $dumpvars(0, tb_reg_vs_wire);
        a = 0; b = 0;
        @(negedge clk);
        @(posedge clk); #1;
        expected_ff = 1'b0;

        // Four input combinations, each applied between two clock edges.
        for (i = 0; i < 4; i = i + 1) begin
            @(negedge clk);
            {a, b} = i[1:0];
            #1;
            // The two combinational outputs follow at once.
            check(y_assign, a & b, "assign now");
            check(y_comb,   a & b, "reg comb now");
            // The flip-flop still holds what it sampled at the last edge.
            check(y_ff, expected_ff, "ff holds");
            @(posedge clk); #1;
            expected_ff = a & b;
            check(y_ff, expected_ff, "ff updated");
        end

        // Change the inputs twice inside one clock period: only the edge counts.
        @(negedge clk);
        a = 1; b = 1; #1;
        check(y_comb, 1'b1, "comb follows");
        a = 1; b = 0; #1;
        check(y_comb, 1'b0, "comb follows");
        $display("  mid-cycle: a=%b b=%b -> assign=%b comb=%b ff=%b (held)",
                 a, b, y_assign, y_comb, y_ff);
        @(posedge clk); #1;
        check(y_ff, 1'b0, "ff sampled");

        $display("PASS: reg vs wire (%0d checks)", checks);
        $finish;
    end

    initial begin
        #2000;
        $fatal(1, "FAIL: testbench timeout");
    end
endmodule
`default_nettype wire

作られません。always @* の中で、どの経路でも y に代入していれば、入力から出力までが組合せ回路になります。reg と宣言していても同じです。ただし、条件によって代入しない経路があると、前の値を保つ必要が生じて意図しないラッチになります（応用実験5で実験できます）。最終的に何が作られたかは、合成レポートでFFの数を見て確認してね。

`timescale 1ns/1ps
`default_nettype none
// Two quiet traps: the width of the assignment target decides the width of
// the calculation, and one unsigned operand makes the whole comparison unsigned.
module width_and_sign (
    input  wire        [3:0] a,
    input  wire        [3:0] b,
    input  wire signed [3:0] sa,
    input  wire        [3:0] ub,
    output wire        [3:0] sum_narrow,
    output wire        [4:0] sum_wide,
    output wire              gt_mixed,
    output wire              gt_signed
);
    assign sum_narrow = a + b;              // 4-bit target: the carry is dropped
    assign sum_wide   = a + b;              // 5-bit target: the carry is kept

    assign gt_mixed  = (sa > ub);           // ub is unsigned -> unsigned compare
    assign gt_signed = (sa > $signed(ub));  // both signed -> signed compare
endmodule
`default_nettype wire

`timescale 1ns/1ps
`default_nettype none
// 256 combinations for the width half, 16 for the sign half.
module tb_width_and_sign;
    reg [3:0] a, b;
    reg signed [3:0] sa;
    reg [3:0] ub;
    wire [3:0] sum_narrow;
    wire [4:0] sum_wide;
    wire gt_mixed, gt_signed;
    reg [4:0] want_wide;
    integer checks = 0;
    integer differ_sign = 0;
    integer i, j;

    width_and_sign dut(.a(a), .b(b), .sa(sa), .ub(ub),
                       .sum_narrow(sum_narrow), .sum_wide(sum_wide),
                       .gt_mixed(gt_mixed), .gt_signed(gt_signed));

    task check;
        input [4:0] actual, expected;
        input [8*12-1:0] label;
        begin
            checks = checks + 1;
            if (actual !== expected)
                $fatal(1, "FAIL: check=%0d %0s a=%b b=%b sa=%b actual=%b expected=%b",
                       checks, label, a, b, sa, actual, expected);
        end
    endtask

    initial begin
        $dumpfile("width_and_sign.vcd");
        $dumpvars(0, tb_width_and_sign);
        sa = 4'd0; ub = 4'd0;

        // Width: the same expression, two different target widths.
        for (i = 0; i < 16; i = i + 1) begin
            for (j = 0; j < 16; j = j + 1) begin
                a = i[3:0]; b = j[3:0];
                #1;
                want_wide = i + j;
                check({1'b0, sum_narrow}, {1'b0, want_wide[3:0]}, "narrow");
                check(sum_wide, want_wide, "wide");
                #1;
            end
        end
        a = 4'd15; b = 4'd1; #1;
        $display("  15 + 1 -> narrow=%0d (%b)  wide=%0d (%b)",
                 sum_narrow, sum_narrow, sum_wide, sum_wide);

        // Sign: the same bits compared two ways, against zero.
        ub = 4'd0;
        for (i = 0; i < 16; i = i + 1) begin
            sa = i[3:0];
            #1;
            check({4'd0, gt_mixed},  {4'd0, (i[3:0] > 4'd0)},        "mixed");
            check({4'd0, gt_signed}, {4'd0, ($signed(i[3:0]) > 0)},  "signed");
            if (gt_mixed !== gt_signed) differ_sign = differ_sign + 1;
            #1;
        end
        sa = -4'sd1; ub = 4'd0; #1;
        $display("  sa=%b (-1) vs ub=0 -> mixed=%b signed=%b", sa, gt_mixed, gt_signed);
        $display("  mixed and signed disagree on %0d of 16 values", differ_sign);

        $display("PASS: width and sign (%0d checks)", checks);
        $finish;
    end

    initial begin
        #20000;
        $fatal(1, "FAIL: testbench timeout");
    end
endmodule
`default_nettype wire

受ける変数を9ビットで宣言すれば足ります。wire [8:0] s = a + b; のように、代入先が9ビットなら計算も9ビットで行われます。先に {1'b0, a + b} と書くと、括弧の中が8ビットで計算されてから広げられるので、桁上げは失われます。上の実験で検出した誤りがこれです。符号付きの場合は、両辺の符号をそろえることも忘れないでね。桁あふれの扱いはC3の加算器の実習でも確かめられます。