論理回路の基礎

`timescale 1ns/1ps
`default_nettype none
// Each bit pairs the two sides of one law from the L1 tables.
// lhs[n] and rhs[n] must be equal for every input combination.
module boolean_laws (
    input  wire a,
    input  wire b,
    input  wire c,
    output wire [17:0] lhs,
    output wire [17:0] rhs
);
    // AND laws
    assign lhs[0]  = a & 1'b0;        assign rhs[0]  = 1'b0;              // A*0 = 0
    assign lhs[1]  = a & 1'b1;        assign rhs[1]  = a;                 // A*1 = A
    assign lhs[2]  = a & a;           assign rhs[2]  = a;                 // A*A = A
    assign lhs[3]  = a & ~a;          assign rhs[3]  = 1'b0;              // A*/A = 0
    // OR laws
    assign lhs[4]  = a | 1'b0;        assign rhs[4]  = a;                 // A+0 = A
    assign lhs[5]  = a | 1'b1;        assign rhs[5]  = 1'b1;              // A+1 = 1
    assign lhs[6]  = a | a;           assign rhs[6]  = a;                 // A+A = A
    assign lhs[7]  = a | ~a;          assign rhs[7]  = 1'b1;              // A+/A = 1
    // commutative
    assign lhs[8]  = a & b;           assign rhs[8]  = b & a;             // AB = BA
    assign lhs[9]  = a | b;           assign rhs[9]  = b | a;             // A+B = B+A
    // associative
    assign lhs[10] = (a & b) & c;     assign rhs[10] = a & (b & c);
    assign lhs[11] = (a | b) | c;     assign rhs[11] = a | (b | c);
    // distributive
    assign lhs[12] = a & (b | c);     assign rhs[12] = (a & b) | (a & c);
    assign lhs[13] = a | (b & c);     assign rhs[13] = (a | b) & (a | c);
    // absorption
    assign lhs[14] = a & (a | b);     assign rhs[14] = a;
    assign lhs[15] = a | (a & b);     assign rhs[15] = a;
    // De Morgan
    assign lhs[16] = ~(a & b);        assign rhs[16] = ~a | ~b;
    assign lhs[17] = ~(a | b);        assign rhs[17] = ~a & ~b;
endmodule
`default_nettype wire

`timescale 1ns/1ps
`default_nettype none
// Drives every combination of a, b and c and compares both sides of all
// 18 laws. 8 combinations x 18 laws = 144 checks.
module tb_boolean_laws;
    reg a, b, c;
    wire [17:0] lhs, rhs;
    integer checks = 0;
    integer i, law;

    boolean_laws dut(.a(a), .b(b), .c(c), .lhs(lhs), .rhs(rhs));

    task check_all;
        begin
            for (law = 0; law < 18; law = law + 1) begin
                checks = checks + 1;
                if (lhs[law] !== rhs[law])
                    $fatal(1, "FAIL: law=%0d a=%b b=%b c=%b lhs=%b rhs=%b",
                           law, a, b, c, lhs[law], rhs[law]);
            end
        end
    endtask

    initial begin
        $dumpfile("boolean_laws.vcd");
        $dumpvars(0, tb_boolean_laws);
        $display("  a b | ~(a.b)  /a+/b | ~(a+b)  /a./b");
        for (i = 0; i < 8; i = i + 1) begin
            {a, b, c} = i[2:0];
            #1;
            check_all;
            if (c == 1'b0)
                $display("  %b %b |   %b       %b   |   %b       %b",
                         a, b, lhs[16], rhs[16], lhs[17], rhs[17]);
            #1;
        end
        $display("PASS: boolean laws (%0d checks)", checks);
        $finish;
    end

    initial begin
        #1000;
        $fatal(1, "FAIL: testbench timeout");
    end
endmodule
`default_nettype wire