Verilog記述テクニック集

`timescale 1ns/1ps
`default_nettype none
// The same patterns written with case, casez and casex.
// The patterns use ? so the differences show up directly.
module case_variants (
    input  wire [3:0] sel,
    output reg  [1:0] y_case,
    output reg  [1:0] y_casez,
    output reg  [1:0] y_casex
);
    always @* begin
        case (sel)                 // exact match only; ? is z here
            4'b1???: y_case = 2'd3;
            4'b01??: y_case = 2'd2;
            4'b001?: y_case = 2'd1;
            default: y_case = 2'd0;
        endcase
    end

    always @* begin
        casez (sel)                // z is don't care on BOTH sides; ? denotes z
            4'b1???: y_casez = 2'd3;
            4'b01??: y_casez = 2'd2;
            4'b001?: y_casez = 2'd1;
            default: y_casez = 2'd0;
        endcase
    end

    always @* begin
        casex (sel)                // x and z are don't care on BOTH sides
            4'b1???: y_casex = 2'd3;
            4'b01??: y_casex = 2'd2;
            4'b001?: y_casex = 2'd1;
            default: y_casex = 2'd0;
        endcase
    end
endmodule
`default_nettype wire

`timescale 1ns/1ps
`default_nettype none
// 16 known inputs, then inputs that contain x.
module tb_case_variants;
    reg [3:0] sel;
    wire [1:0] y_case, y_casez, y_casex;
    reg [1:0] want_priority;
    integer checks = 0;
    integer i;

    case_variants dut(.sel(sel), .y_case(y_case), .y_casez(y_casez), .y_casex(y_casex));

    task check;
        input [1:0] actual, expected;
        input [8*10-1:0] label;
        begin
            checks = checks + 1;
            if (actual !== expected)
                $fatal(1, "FAIL: check=%0d %0s sel=%b actual=%b expected=%b",
                       checks, label, sel, actual, expected);
        end
    endtask

    initial begin
        $dumpfile("case_variants.vcd");
        $dumpvars(0, tb_case_variants);

        // Known inputs: casez and casex agree, plain case never matches.
        for (i = 0; i < 16; i = i + 1) begin
            sel = i[3:0];
            #1;
            want_priority = sel[3] ? 2'd3 : sel[2] ? 2'd2 : sel[1] ? 2'd1 : 2'd0;
            check(y_case,  2'd0,          "case");
            check(y_casez, want_priority, "casez");
            check(y_casex, want_priority, "casex");
            #1;
        end

        // An input that contains x.
        sel = 4'bxx01; #1;
        $display("  sel=%b -> case=%0d casez=%0d casex=%0d", sel, y_case, y_casez, y_casex);
        check(y_case,  2'd0, "x case");
        check(y_casez, 2'd0, "x casez");
        check(y_casex, 2'd3, "x casex");   // matched 1??? although bit3 is unknown

        sel = 4'b0x10; #1;
        $display("  sel=%b -> case=%0d casez=%0d casex=%0d", sel, y_case, y_casez, y_casex);
        check(y_case,  2'd0, "x case");
        check(y_casez, 2'd0, "x casez");
        check(y_casex, 2'd2, "x casex");   // matched 01?? although bit2 is unknown

        // z in the expression: casez ignores it too, and plain case can match
        // because ? in a pattern is literally z.
        sel = 4'bz001; #1;
        $display("  sel=%b -> case=%0d casez=%0d casex=%0d", sel, y_case, y_casez, y_casex);
        check(y_case,  2'd0, "z case");
        check(y_casez, 2'd3, "z casez");   // the z in the expression is ignored
        check(y_casex, 2'd3, "z casex");

        sel = 4'b1zzz; #1;
        $display("  sel=%b -> case=%0d casez=%0d casex=%0d", sel, y_case, y_casez, y_casex);
        check(y_case,  2'd3, "z case");    // ? is z, so this is an exact match
        check(y_casez, 2'd3, "z casez");
        check(y_casex, 2'd3, "z casex");

        $display("PASS: case variants (%0d checks)", checks);
        $finish;
    end

    initial begin
        #2000;
        $fatal(1, "FAIL: testbench timeout");
    end
endmodule
`default_nettype wire

x を無視させたくないなら casez です。casex は式の側の不明値まで don't care にしてしまうので、上で見たように「不明なまま分岐が選ばれる」状態を作ります。どうしても入力側の不明値を扱いたい場合は、その条件が起こりうるのかを先に仕様で確かめてね。また、? を書いても case では don't care にならない点にも注意です。合成時の扱いはツールにも依存するので、使うなら対象ツールの資料も確認しよう。