Verilog基本文法（後編）

`timescale 1ns/1ps
`default_nettype none
// Two traps that compile without an error.
//   select_narrow : a function with no width returns one bit
//   select_wide   : the same body with an explicit 2-bit return
//   and g_ok      : the first port of a gate primitive is its output
module syntax_traps (
    input  wire       sel,
    input  wire [1:0] d0,
    input  wire [1:0] d1,
    input  wire       ga,
    input  wire       gb,
    output wire [1:0] y_narrow,
    output wire [1:0] y_wide,
    output wire       y_gate
);
    function select_narrow;
        input s;
        input [1:0] a, b;
        begin
            select_narrow = s ? b : a;
        end
    endfunction

    function [1:0] select_wide;
        input s;
        input [1:0] a, b;
        begin
            select_wide = s ? b : a;
        end
    endfunction

    assign y_narrow = select_narrow(sel, d0, d1);
    assign y_wide   = select_wide(sel, d0, d1);

    wire a_int, b_int;
    assign a_int = ga;
    assign b_int = gb;
    and g_ok(y_gate, a_int, b_int);
endmodule
`default_nettype wire

`timescale 1ns/1ps
`default_nettype none
// sel 2 x d0 4 x d1 4 = 32 patterns for the two functions, then 4 for the gate.
module tb_syntax_traps;
    reg sel;
    reg [1:0] d0, d1;
    reg ga, gb;
    wire [1:0] y_narrow, y_wide;
    wire y_gate;
    reg [1:0] want;
    integer checks = 0;
    integer i;

    syntax_traps dut(.sel(sel), .d0(d0), .d1(d1), .ga(ga), .gb(gb),
                     .y_narrow(y_narrow), .y_wide(y_wide), .y_gate(y_gate));

    task check;
        input [1:0] actual, expected;
        input [8*8-1:0] label;
        begin
            checks = checks + 1;
            if (actual !== expected)
                $fatal(1, "FAIL: check=%0d %0s sel=%b d0=%b d1=%b actual=%b expected=%b",
                       checks, label, sel, d0, d1, actual, expected);
        end
    endtask

    initial begin
        $dumpfile("syntax_traps.vcd");
        $dumpvars(0, tb_syntax_traps);
        ga = 0; gb = 0;
        for (i = 0; i < 32; i = i + 1) begin
            {sel, d0, d1} = i[4:0];
            #1;
            want = sel ? d1 : d0;
            check(y_wide, want, "wide");
            // The narrow function keeps only the low bit; the upper bit is lost.
            check(y_narrow, {1'b0, want[0]}, "narrow");
            if (sel == 1'b1 && d0 == 2'b01 && d1 == 2'b10)
                $display("  sel=%b d0=%b d1=%b -> wide=%b narrow=%b (want %b)",
                         sel, d0, d1, y_wide, y_narrow, want);
            #1;
        end

        for (i = 0; i < 4; i = i + 1) begin
            {ga, gb} = i[1:0];
            #1;
            check({1'b0, y_gate}, {1'b0, ga & gb}, "gate");
            #1;
        end

        $display("PASS: syntax traps (%0d checks)", checks);
        $finish;
    end

    initial begin
        #2000;
        $fatal(1, "FAIL: testbench timeout");
    end
endmodule
`default_nettype wire

戻り値は1ビットなので、合計の最下位ビットだけが残ります。同じ形で試したところ、こうなりました（2026年10月27日 Icarus Verilog 13.0）。

3+5  : narrow=0 (00000000)  wide=8 (00001000)
3+4  : narrow=1 (00000001)  wide=7 (00000111)

3 + 5 = 8 のつもりでも 0 が返ります（8は 1000 で最下位が0）。3 + 4 = 7 なら最下位が1なので 1 が返り、一見「それらしい値」に見えるのも厄介なところだよ。呼び出し側の変数を8ビットにしても直りません。直すのは宣言側で、function [7:0] add8; のように返す幅を書きます。引数の幅、中間計算の幅、呼び出し側の幅も合わせて見直してね。ビット幅の扱いは文法実験4、桁あふれの扱いはC3の実習にもあります。